A 12-bit, 100 ks/s, pvt robust sar adc in 65 nm cmos process

Abstract

We present a highly robust 12-bit, 100 kS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) that excels in mitigating the effects of mismatch, temperature variations and process corners. A modified hybrid switching method is developed in design of the Capacitive Digital-to-Analog Converter (C-DAC) that saves 17 % of the DAC power consumption. Furthermore, we utilize a switched local feedback loop in the pre-amplifier circuit of the comparator that significantly minimizes the offset. Using this technique, the 3-sigma offset is reduced from 11.33 mV to 0.37 mV. Moreover, a high performance latched-based Bit Slice Unit (BSU) is proposed to preserve the successive codes during each conversion. Designed in 65 nm CMOS technology, the ADC operates in -55 degrees C to +125 degrees C temperature range, consuming only 1.55 mu W with a 0.7V supply voltage and occupying a 0.6 mm2 area.